CD4073B Triple 3-Input CMOS AND Gate DIP-14

CD4073B Triple 3-Input CMOS AND Gate DIP-14

Technical Datasheet

CD4073B Gates.provide the system ed Inner with direct implementation of the AND function and supplement the existing family of CMOS gates.

• Medium-Speed Operation -TPLH, TPHL=60ns（tsp.）at VDD = 10 V
• 100% tested for quiescent current at 20V Maximum input current of 1μA at 18 V over full pack-temperature range，100 nA at 18 V and 25ºC
• Noise margin（full package-temperature range）

1. 1V at VDD=5V
2. 2V at VDD=10V
3. 2.5V at VDD=15

• Standardized,symmetrical ou taut characteristics
• 5V 10Vand 15V parametric ratings
• Meets all requirements of JEDEC Tentative Tankard