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PIC24FJ256DA210-I/PT TQFP-100

PIC24FJ256DA210-I/PT TQFP-100
PIC24FJ256DA210-I/PT TQFP-100
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The PIC24FJ256DA210 family enhances on the existing line of Microchip‘s 16-bit microcontrollers, adding a new Graphics Controller (GFX) module to interface with a graphical LCD display and also adds large data RAM, up to 96 Kbytes. The PIC24FJ256DA210 family allows the CPU to fetch data directly from an external memory device using the EPMP module.

Key Features

Graphics Controller Features:

  • Three Graphics Hardware Accelerators to Facilitate Rendering of Block Copying, Text and Unpacking of Compressed Data
  • Color Look-up Table (CLUT) with Maximum of 256 Entries
  • 1/2/4/8/16 bits-per-pixel (bpp) Color Depth Set at Run Time

Display Resolution Programmable According to Frame Buffer:

  • Supports direct access to external memory on devices with EPMP
  • Resolution supported is up to 480x272 @ 60 Hz, 16 bpp; 640x480 @ 30 Hz, 16 bpp or 640x480 @ 60 Hz, 8 bpp

Supports Various Display Interfaces:

  • 4/8/16-bit Monochrome STN
  • 4/8/16-bit Color STN
  • 9/12/18/24-bit Color TFT (18 and 24-bit displays are connected as 16-bit, 5-6-5 RGB color format)

Universal Serial Bus Features:

  • USB v2.0 On-The-Go (OTG) Compliant
  • Dual Role Capable – Can act as either Host or Peripheral
  • Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps) USB Operation in Host mode
  • Full-Speed USB Operation in Device mode
  • High-Precision PLL for USB

Supports up to 32 Endpoints (16 bidirectional):

  • USB module can use the internal RAM location from 0x800 to 0xFFFF as USB endpoint buffers
  • On-Chip USB Transceiver with Interface for Off-Chip Transceiver
  • Supports Control, Interrupt, Isochronous and Bulk Transfers
  • On-Chip Pull-up and Pull-Down Resistors

Peripheral Features

Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP), 100-pin devices only:

  • Direct access from CPU with an Extended Data Space (EDS) interface
  • 4, 8 and 16-bit wide data bus
  • Up to 23 programmable address lines
  • Up to 2 chip select lines
  • Up to 2 Acknowledgement lines (one per chip select)
  • Programmable address/data multiplexing
  • Programmable address and data Wait states
  • Programmable polarity on control signals

Peripheral Pin Select:

  • Up to 44 available pins (100-pin devices)
  • Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes)
  • Three I2C™ modules Supporting Multi-Master/Slave modes and 7-Bit/10-Bit Addressing

Four UART modules:

Supports RS-485, RS-232, LIN/J2602 protocols and IrDA®

  • Five 16-Bit Timers/Counters with Programmable Prescaler
  • Nine 16-Bit Capture Inputs, each with a Dedicated Time Base
  • Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base
  • Hardware Real-Time Clock and Calendar (RTCC)
  • Enhanced Programmable Cyclic Redundancy Check (CRC) Generator
  • Up to 5 External Interrupt Sources
  • High-Performance CPU
  • Modified Harvard Architecture
  • Up to 16 MIPS Operation at 32 MHz
  • 8 MHz Internal Oscillator
  • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier
  • 32-Bit by 16-Bit Hardware Divider
  • 16 x 16-Bit Working Register Array
  • C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes
  • Linear Program Memory Addressing, up to 12 Mbytes

Data Memory Addressing, up to 16 Mbytes:

  • 2K SFR space
  • 30K linear data memory
  • 66K extended data memory
  • Remaining (from 16 Mbytes) memory (external) can be accessed using extended data Memory (EDS) and EPMP (EDS is divided into 32-Kbyte pages)


Technical Datasheet

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